A SiCOH BEOL interconnect technology for high density and high performance 65 nm CMOS applications

Abstract

The development and qualification of a 300 mm SiCOH Back End of Line (BEOL) integration for 65 nm bulk and SOI semiconductor product applications is presented. A hierarchical BEOL architecture is employed which allows up to 10 levels of copper metallization with as many as 8 levels built in SiCOH (k ∼3) interlevel dielectric. The interconnect architecture renders this BEOL technology suitable for both high performance microprocessors and high density Application Specific Integrated Circuits (ASICs). Key process integration challenges overcome during the course of qualification are presented. The impact of these process improvements on electrical yield, defect density, reliability, and performance are discussed. © 2006 Materials Research Society.