Publications

8 results for Gerald Matusiewicz

Using CMP model for 45nm/32nm BEOL process and design evaluations
- - Laertis Economikos
  - Jerry Bao
  - et al.
- 2010
- ECS Meeting 2010
Characterization, Modeling and Extraction of Cu Wire Resistance for 65 nm Technology
- - Ning Lu
  - M. Angyal
  - et al.
- 2007
- CICC 2007
A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technology
- - S. Sankaran
  - S. Arai
  - et al.
- 2006
- IEDM 2006
A SiCOH BEOL interconnect technology for high density and high performance 65 nm CMOS applications
- - Matthew Angyal
  - Jason Gill
  - et al.
- 2005
- AMC 2005
65nm CMOS technology for low power applications
- - A. Steegen
  - R. Mo
  - et al.
- 2005
- IEDM 2005
Electrical and reliability evaluation of Cu/Low-k integration: Exploration of PVD barrier/seed and CVD SiC(N,H) cap depositions
- - C.-C. Yang
  - D. Edelstein
  - et al.
- 2004
- ADMETA 2004
90 nm SiCOH technology in 300 mm manufacturing
- - L. Clevenger
  - M. Yoon
  - et al.
- 2004
- ADMETA 2004
A 90nm dual damascene hybrid (organic / inorganic) low-k - Copper BEOL integration scheme
- - T. Dalton
  - A. Cowley
  - et al.
- 2003
- ADMETA 2003