IEDM 2005
Conference paper

65nm CMOS technology for low power applications


This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676μm2 and 0.54μm2 SRAM cells, optimized for performance and density, respectively. The key focus of this technology has been low cost, process simplicity and power reduction. A gate dielectric with an nfet leakage current as low as 15pA/μm and with exceptional reliability characteristics has been demonstrated. Moreover, competitive drive current has been achieved, 725/343uA/um at an off current of 7nA/um for n/pfets at nominal voltage. A pfet performance enhancement of an additional 13% at 7nA/um off current was achieved by using mobility enhancement techniques without adding process complexity. An optimized NiSi process and high angle, low dose halo implants contribute to the reduced junction leakage and GIDL current. © 2005 IEEE.