Etch and Patterning Development for 2nm Node Nanosheet Devices
- Eric Miller
- Indira Seshadri
- et al.
- 2022
- SPIE Advanced Lithography 2022
Publications
Nanosheet Metrology Opportunities for Technology Readiness
- Mary Breton
- Daniel Schmidt
- et al.
- 2021
- SPIE Advanced Lithography 2021
Measuring Local CD Uniformity in EUV vias with scatterometry and machine learning
- Dexin Kong
- Daniel Schmidt
- et al.
- 2020
- SPIE Advanced Lithography 2020
Exploration of pillar local CDU improvement options for AI applications
- Charlie Liu
- Hao Tang
- et al.
- 2020
- SPIE Advanced Lithography 2020
Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyond
- Charlie Liu
- Elliott Franke
- et al.
- 2018
- Nature Electronics
Patents
Self Aligned Conductive Lines
- 05 Mar 2018
- US
- 9911647
Application Of Titanium-oxide As A Patterning Hardmask
- 23 Oct 2017
- US
- 9799534
Self Aligned Conductive Lines
- 09 Oct 2017
- US
- 9786554
Method And Structure For Cut Material Selection
- 02 Oct 2017
- US
- 9779944
Metrology Marks For Unidirectional Grating Superposition Patterning Processes
- 16 Jun 2015
- US
- 9059102
Multi-layer Chip Overlay Target And Measurement
- 30 Sep 2014
- US
- 8847416
Self-calibrated Alignment And Overlay Target And Measurement
- 28 Jan 2014
- US
- 8638438
Multi-layer Chip Overlay Target And Measurement
- 29 Jan 2013
- US
- 8361683
Blog posts
EUV patterning yield breakthrough sets new benchmark for logic scaling
Technical noteNelson Felix and Luciana Meli4 minute read- AI Hardware
- Hardware Technology
- Logic Scaling
- Semiconductors
IBM Research at SPIE 2020: New architectures and fabrications for AI hardware
ResearchNelson Felix4 minute read- AI Hardware
- Semiconductors
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