EUV patterned gate variation reduction in next generation transistor architectures
- Gopal Kenath
- Martin Burkhardt
- et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
Nelson Felix
Title
Director, Technical Business Development - IBM Semiconductors
Publications
Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
- Shogo Mochizuki
- Nicolas Loubet
- et al.
- 2023
- IEDM 2023
Scaling opportunities for Gate-All-Around and beyond: A patterning perspective
- Indira Seshadri
- Eric Miller
- et al.
- 2023
- IEDM 2023
Scaling opportunities for Gate-All-Around: A patterning perspective
- I. Seshadri
- E. Miller
- et al.
- 2023
- IEDM 2023
Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors
- Curtis Durfee
- Ivo Otto
- et al.
- 2023
- ECS Meeting 2023
Epi Source/Drain Damage Mitigation with Inner Spacer and Buffer Optimization in Stacked Nanosheet Gate-All-Around Transistors
- Curtis Durfee
- Ivo Otto
- et al.
- 2023
- SSDM 2023
Advanced BEOL Materials, Processes, and Integration to Reduce Line Resistance of Damascene Cu, Co, and Subtractive Ru Interconnects
- Takeshi Nogami
- Oleg Gluschenkov
- et al.
- 2022
- VLSI Technology and Circuits 2022
Etch and Patterning Development for 2nm Node Nanosheet Devices
- Eric Miller
- Indira Seshadri
- et al.
- 2022
- SPIE Advanced Lithography 2022
Review of nanosheet metrology opportunities for technology readiness
- Mary A. Breton
- Daniel Schmidt
- et al.
- 2022
- JM3
EUV single exposure via patterning at aggressive pitch
- Jing Guo
- Jennifer Church
- et al.
- 2021
- SPIE Advanced Lithography 2021
Patents
- US
- 12019376
- US
- 12021135
- CN
- ZL 2018 8 0081456.1
- US
- 11804401
- US
- 11699592
- US
- 11695059
- US
- 11681213
- US
- 11682558
- US
- 11646221
- JP
- 7268946
Blog posts
IBM and Albany partners unlock new yield benchmarks for EUV patterning
Technical noteLuciana Meli and Nelson FelixEUV patterning yield breakthrough sets new benchmark for logic scaling
Technical noteNelson Felix and Luciana Meli4 minute readIBM Research at SPIE 2020: New architectures and fabrications for AI hardware
ResearchNelson Felix4 minute read
Top collaborators
LM
Luciana Meli
Senior Manager: Patterning & Metrology
NL
Nicolas Loubet
STSM, Advanced Logic Technology Research
MB
Mary Breton
Technical Assistant to Huiming Bu | Semiconductor Enablement Program Management & Infrastructure
HB
Huiming Bu
Vice President: IBM Semiconductors Global R&D and Albany Operations