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IBM Research at SPIE 2020: New architectures and fabrications for AI hardware

IBM Research had 21 papers accepted to SPIE, and will present on EUV lithography, patterning materials, novel device integration, and more.

Group photo of the IBM team members presenting at SPIE Advanced Lithography 2020.

IBM Research had 21 papers accepted to SPIE, and will present on EUV lithography, patterning materials, novel device integration, and more.

In the last decade, IBM has pioneered AI hardware technologies that have produced the top two supercomputers and most-secure enterprise platform in the world. At this year’s SPIE Advanced Lithography conference (February 24-27), IBM Research will continue this tradition of developing pioneering technologies through new research in AI hardware, alongside continued innovation in logic transistor scaling. These advances are part of IBM Research’s mission to deliver leading-edge semiconductor technology that enables future generations of computational systems to handle tomorrow’s needs. IBM Research had 21 papers accepted to SPIE, and throughout the four-day conference IBM researchers will present on topics ranging from EUV lithography, patterning materials, metrology, etch, selective deposition, and novel device integration.

In opening plenary session, IBM Fellow Evangelos Eleftheriou will describe in “In-memory computing for AI applications” why traditional von Neumann semiconductor systems run out of steam when trying to enable AI workloads, and how to address this issue. By demonstrating the feasibility of computing in memory, he shows how machine learning tasks can be made many times faster and with lower power consumption with this approach. Evangelos will demonstrate applicability of this approach to tackle a wide variety of small- and large-scale computational issues, such as ultra-low-power inference engines; optimization solvers, including compressed sensing and sparse coding; linear solvers and temporal correlation detection. Thus, by augmenting conventional computing systems, in-memory computing could help achieve orders of magnitude improvement in performance and efficiency.

Other AI hardware talks present new research in the fabrications of architecture. They include:

  • “Exploration of pillar local CDU improvement options for AI applications”: IBM researcher Charlie Liu will present four promising options for patterning memory elements with increasing perfection. By doing so, Charlie highlights the breadth of IBM’s expertise in patterning, and how it can be brought to bear in new areas such as memory-like constructs. Through this work, he demonstrates size perfection greater than 95%, enabling the ability to use these techniques for AI hardware manufacture.
  • “Challenges in the patterning of RRAM devices for analog computing applications”: IBM researcher Iqbal Saraf shows some of the innovation in plasma etch technology required to create these delicate structures via the harsh process of plasma etching. Through this work, Iqbal shows that the ability to store different model training “weights” is still preserved after the patterning process.
  • “CMOS scaling roadmap, Nanosheet FET, AI chips”: Huiming Bu, director of Advanced Logic & Memory Technology Research at IBM, will demonstrate how continued advancements in traditional logic transistor scaling are still required in an AI world, and how this is epitomized in the Nanosheet transistor architecture announced by IBM a couple of years ago. Heavily dependent on the semiconductor industry’s latest patterning technique of extreme ultraviolet (EUV) lithography to create the features required, Nanosheet transistors allow for >30% faster and more-efficient logic computation than current state-of-the-art FinFET devices. IBM is also advancing research in EUV lithography. These presentations include:
  • “A comparative analysis of EUV sheet and gate patterning for beyond 7nm gate all around stacked nanosheet FET’s”: IBM researcher Indira Seshadri details how the fine patterns enabled by EUV are critical to this next inflection point in logic scaling that will be available in consumer and enterprise devices in the next 2-3 years. Using the resolution and simplified patterning enabled by EUV, Indira demonstrates methods to create both the wide sheets required for high-performance devices, and the small structures required for memory, in the same process, representing a new use case for EUV patterning.
  • “Fundamental Characterization of Stochastic Variation in EUV Patterning”: IBM researcher Jen Church attempts to push EUV lithography to its limits, demonstrating high yield for EUV-printed wiring at pitches below 32 nanometers, which is smaller than any currently available technology. This data shows some surprising results, including the lack of correlation between wiring line roughness and yield, and how small changes in materials or lithography imaging conditions can lead to huge benefits in yield, with high yield even shown for wiring pitches of 30 nanometers.
  • “High-Z metal-based underlayer to improve EUV stochastics”: IBM researcher Anuja De Silva demonstrates how to further improve on this yield and performance by intelligent design of the materials used for EUV patterning. Through intelligent design of a highly EUV-absorbing underlayer, as well as careful engineering of chemical surface interactions, Anuja will show consistent yields of 100% for 30 nanometer pitch wiring, at lower exposure energies than traditional approaches.

As the demand for AI-enhanced computing continues to grow, innovation is critical to ensure that semiconductor hardware can keep pace. By continuing to push the boundaries of both logic scaling and new concepts in AI hardware, IBM and its partners continue to drive the semiconductor roadmap ahead for the next decade.