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JM3
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Review of nanosheet metrology opportunities for technology readiness

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Abstract

Over the past several years, stacked nanosheet gate-all-around (GAA) transistors captured the focus of the semiconductor industry and have been identified as the lead architecture to continue logic complementary metal-oxide-semiconductor scaling beyond 5 nm node. The fabrication of GAA devices requires specific integration modules. From very early processing points, these structures require complex metrology to fully characterize the three-dimensional parameter set. As the technology progresses through research and development cycles and is poised to transition to manufacturing, there are many opportunities and challenges that still remain for in-line metrology. Especially valuable are measurement techniques that are non-destructive, fast, and provide multi-dimensional feedback, where reducing dependencies on offline techniques has a direct impact on the frequency of cycles of learning. More than previous technologies, then, nanosheet technology may be when some offline techniques transition from the lab to the fab, as certain critical measurements need to be monitored in real time. Thanks to the computing revolution the semiconductor industry enabled, machine learning has begun to permeate in-line disposition, and hybrid metrology systems continue to advance. Of course, metrology solutions and methodologies developed for prior technologies will also still have a large role in the characterization of these structures, as effects such as line edge roughness, pitch walk, and defectivity continue to be managed. We review related prior studies and advocate for future metrology development that ensures nanosheet technology has the in-line data necessary for success.

Date

18 Apr 2022

Publication

JM3

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