SSDM 2023
Conference paper

Epi Source/Drain Damage Mitigation with Inner Spacer and Buffer Optimization in Stacked Nanosheet Gate-All-Around Transistors


Abstract In this paper, we characterize some key strategies to mitigate pFET source/drain (S/D) epi damage during channel release in nanosheet devices without degrading performance by optimizing the inner spacer (IS) length or introducing a buffer prior to SiGe:B S/D deposition. As expected, the DC performance improves with decreased IS length driven by a reduction in Rext. In addition, we have benchmarked several SiGe etch chemistries with increased process margin to prevent S/D damage and characterize the corresponding device performance. 1. Introduction Transition from tri-gate FinFET devices to gate-all-around (GAA) nanosheet (NS) devices offers im-proved electrostatic control, short channel control, effective capacitance and drive current [1-5]. However, it also poses significant challenges in enabling GAA architecture, which involves two key modules: (1) inner spacer (IS) formation, and (2) channel formation [6] (Fig. 1(a)-(d)). A critical chal-lenge is preventing source/drain (S/D) epi damage (Fig. 2), which can occur if the S/D epi is exposed to the etchants during channel release (CR) etch since CR requires 200% overetch margin to release all sheets across a wide range of sheet widths (WNS) [6,7]. This improvement in S/D epi reten-tion can be achieved by (1) targeting IS length to provide a sufficient physical barrier to prevent etchant permeation through the IS, (2) using a buffer before S/D epi deposition as an additional barrier, (3) optimizing the IS shape from a rounded profile to a square profile to prevent etch pathways around the IS and enable reduction in IS length, and (4) tuning CR chemistry to increase selectivity to SiGe:B (Fig. 1(e)-(g)). 2. Experimental Setup Long-channel (Lg=100nm) devices with WNS=20-100nm were integrated on (100) Si substrates. Our historical SiB S/D epi process is not susceptible to damage due to the high se-lectivity of CR etches to SiB. Therefore, to characterize the CR process window, we developed a selective SiGe:B S/D epi process, which grows directly from the Si substrate as well as from the (110) Si channel tips. As expected, the Si-Ge:B process showed improved device Ron due to better B solubility in Ge. The large S/D epi volume from the large canyon space and nucleation from the substrate introduce significant strain in these long channel devices, resulting in increased gmmax over devices with SiB S/D epi (Fig. 3). 3. Damage Mitigation using IS, buffers, and CR IS lengths ranging from 3 to 9nm were used to evaluate S/D damage during CR, both with and without buffers, and for various CR etch chemistries. For low IS, S/D epi damage is visible, but as the IS length increases above a critical val-ue or when a buffer is deposited prior to S/D epi deposition, the damage is eliminated (Figs. 2, 4 and 5). Above this criti-cal thickness, we see comparable Vt vs. IS length with and without buffers (Fig. 6). Furthermore, we observe noticeable reduction in the leakage current (Fig. 7). S/D damage was evaluated for three different CR chemistries, Processes A, B and C, as a function of IS length. Process C was robust to S/D damage for all IS lengths down to 0nm without a buffer, while Process B showed the most degradation (Fig. 8). Dit, an indicator of Si channel quality, was compared for all processes (Fig. 9). For the three CR chemistries studied, there is negligible impact to Vt, Ron, peak mobility for the two IS lengths con-sidered here (Fig. 10). Tinv and Toxgl also indicate no Si chan-nel degradation and similar surface quality (Fig. 11) across CR chemistries, with comparable breakdown voltage (VBD). Negative bias temperature instability (NBTI) shows good reliability for all CR processes. (Fig. 12). 4. Conclusions Developing a robust pFET device requires optimized IS and CR processes to ensure no damage to the S/D epi while optimizing device performance. Critical factors are CR chemistry and IS depth, which determine device perfor-mance; IS depth defines the gate length and strongly im-pacts device performance, while CR chemistry enables a wide range of device geometries with pristine Si surfaces prior to high k metal gate formation. We have demonstrated a robust process window to S/D damage with improvements Ron, Vt, and Ioff and reduced device variability and stable NBTI. Understanding the process window and interactions between these parameters is important in tuning and scaling for future technology nodes.