This metric is a significant step along the line of a manufacturing-ready yield, which requires unbroken line yields over 1 meter in length at these dimensions! It’s the equivalent of paving a two-lane highway more than once around the world without any deviations in placement and size more than a foot.
This breakthrough represents a new high watermark in terms of logic scaling with EUV patterning, and it nearly realizes the full potential of this new EUV exposure tool. Achieving such yields at these small dimensions does not come from finding a magic material or process, but rather an exercise in co-optimization across all the contributors to patterning success. These innovations include creating mask templates that have the right fidelity of pattern shapes, finding the right illumination conditions to project that pattern onto the silicon wafer with maximum contrast, optimizing and matching the right photoresists and films that realize this pattern on the silicon wafer, and iterating on the right etch process that transfers this pattern into the silicon wafer with maximum yield.
The continuous cycles of co-optimization, along with the improvement in resolution of our latest EUV lithography system, have led to a one-thousand-fold decrease in the density of defects that detract from the yield of the functioning chip, with a line-edge roughness (LER) below 1.5 nanometers, a key metric for achieving yields for future nodes.
This breakthrough firmly extends the capability of single-expose EUV patterning to the 5nm node and below, and it will be used as the platform IBM and partners use to extend EUV patterning to even smaller nodes.
The IBM Hybrid Cloud research model of partnering with key hardware suppliers using manufacturing-ready milestones like chip yield was necessary for success. In fact, this breakthrough in EUV patterning performance is the result of collaboration with many of IBM’s semiconductor research partners. As our research continues to drive the roadmap for logic scaling in support of the diversified computing platform of the future, our open model of collaboration with our partners will continue to be used to demonstrate the key elements to further increases in compute power and efficiency.
Learn more about the deep research into the future of semiconductors that EUV lithography is enabling at our research facility in Albany, New York.