Technical note
4 minute read

EUV patterning yield breakthrough sets new benchmark for logic scaling

This breakthrough in EUV lithography firmly extends the capability of single-expose EUV benchmark patterning to the 5nm node and below.

This breakthrough in EUV lithography firmly extends the capability of single-expose EUV benchmark patterning to the 5nm node and below.

IBM has a long history of being at the forefront of patterning advancements that drive semiconductor logic scaling to ever-smaller dimensions in keeping with Moore’s Law. From the invention of the chemically-amplified photoresist, through the early demonstration and adoption of immersion lithography, IBM’s leadership in patterning has spanned decades. This leadership was recently underscored by the announcement of the new POWER10 processor, the latest to enable enterprise-grade Hybrid Cloud compute at three times the previous processor energy efficiency. This ability to shrink transistor patterning to smaller and smaller dimensions, thousands of times thinner than the human hair, is correlated to the wavelength of light used to expose the patterning. These advances provide critical hardware needs for the IBM Hybrid Cloud.

For the last half-decade, the industry has focused on using Extreme Ultraviolet (EUV) lithography light at 13.5nm wavelength to achieve this. In a single exposure, EUV lithography can create a high-resolution pattern that is unattainable by prior semiconductor patterning processes. However, the technology required to achieve this three-fold increase in resolution is more complex than anything preceding it, requiring intensive research and development effort.

Back in 2014, IBM was the first to publicly announce the installation and operation of the state-of-the-art EUV lithography system, the ASML NXE3300. This particular system was one of the key enablers in the announcement of the first 7nm FinFET transistor logic using EUV in 2015 and in the demonstration of the first Nanosheet transistor logic in 2017. Since then, the semiconductor industry has consolidated on using EUV technology for the 7nm node and below (including IBM’s POWER10, the first IBM processor to use EUV lithography) and Nanosheets, otherwise known and lateral gate all-around (GAA), for the next transistor type beyond FinFET.

The NXE3300 EUV system was the workhorse lithography tool for IBM Hybrid Cloud scaling research. After six years of operation (the longest continuously-running EUV tool at a customer site), IBM, in conjunction with New York State, has replaced this with the latest EUV system, the NXE3400. Now, this system is fully operational in a state-of-the-art semiconductor research fab on the SUNY Poly campus in Albany, enabling logic research for the next decade to come.

In conjunction with the installation of this new EUV capability in New York State, today we are announcing significant yields for transistor interconnects at 28 nanometer pitch, which corresponds to a 14-nanometer-wide copper interconnect line. Built on our prior work of showing significant yield at larger pitches compatible with the 7nm and 5nm nodes, we were able to demonstrate yield of an unbroken 14 nanometer line, which supports logic scaling below the 5nm node, at lengths more than 1 centimeter (10 million nanometers) at many points across a silicon wafer.

Demonstration design of perfectly-yielding interconnect lines almost 1 million times as long as they are wide, at 28 nanometer pitch (line is 14 nanometers wide).Demonstration design of perfectly-yielding interconnect lines almost 1 million times as long as they are wide, at 28 nanometer pitch (line is 14 nanometers wide).

This metric is a significant step along the line of a manufacturing-ready yield, which requires unbroken line yields over 1 meter in length at these dimensions! It’s the equivalent of paving a two-lane highway more than once around the world without any deviations in placement and size more than a foot.

This breakthrough represents a new high watermark in terms of logic scaling with EUV patterning, and it nearly realizes the full potential of this new EUV exposure tool. Achieving such yields at these small dimensions does not come from finding a magic material or process, but rather an exercise in co-optimization across all the contributors to patterning success. These innovations include creating mask templates that have the right fidelity of pattern shapes, finding the right illumination conditions to project that pattern onto the silicon wafer with maximum contrast, optimizing and matching the right photoresists and films that realize this pattern on the silicon wafer, and iterating on the right etch process that transfers this pattern into the silicon wafer with maximum yield.

The continuous cycles of co-optimization, along with the improvement in resolution of our latest EUV lithography system, have led to a one-thousand-fold decrease in the density of defects that detract from the yield of the functioning chip, with a line-edge roughness (LER) below 1.5 nanometers, a key metric for achieving yields for future nodes.

This breakthrough firmly extends the capability of single-expose EUV patterning to the 5nm node and below, and it will be used as the platform IBM and partners use to extend EUV patterning to even smaller nodes.

The IBM Hybrid Cloud research model of partnering with key hardware suppliers using manufacturing-ready milestones like chip yield was necessary for success. In fact, this breakthrough in EUV patterning performance is the result of collaboration with many of IBM’s semiconductor research partners. As our research continues to drive the roadmap for logic scaling in support of the diversified computing platform of the future, our open model of collaboration with our partners will continue to be used to demonstrate the key elements to further increases in compute power and efficiency.

Learn more about the deep research into the future of semiconductors that EUV lithography is enabling at our research facility in Albany, New York.