SPIE Advanced Lithography + Patterning 2024
Conference paper

EUV patterned gate variation reduction in next generation transistor architectures

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Transistor architectures below the 7 nm node are significantly enabled by EUV lithography, with single exposure EUV processes simplifying small pitch patterning processes. However, EUV stochastics are a significant hurdle in meeting aggressive process assumption targets and achieving high yields. In particular, line edge roughness and line width roughness (LER and LWR) at EUV patterned gate have been identified as key limiters of device performance and yield within these nodes. Here, we study the impact of different illumination schemes on gate LER and LWR. We specifically utilize NILS to target LER and LWR reduction, with high NILS observed to primarily reduce high frequency roughness. Post etch, a largely illumination independent reduction in the mid and high frequency regimes is observed. Finally, impact of illumination on long channel gate patterning is assessed and a NILS independent LWR response is observed both post development and etch.