Nelson Felix

Title

Director, Technical Business Development - IBM Semiconductors

Publications

EUV patterned gate variation reduction in next generation transistor architectures
- - Gopal Kenath
  - Martin Burkhardt
  - et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
- - Shogo Mochizuki
  - Nicolas Loubet
  - et al.
- 2023
- IEDM 2023
Scaling opportunities for Gate-All-Around: A patterning perspective
- - I. Seshadri
  - E. Miller
  - et al.
- 2023
- IEDM 2023
Scaling opportunities for Gate-All-Around and beyond: A patterning perspective
- - Indira Seshadri
  - Eric Miller
  - et al.
- 2023
- IEDM 2023
Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors
- - Curtis Durfee
  - Ivo Otto
  - et al.
- 2023
- ECS Meeting 2023
Epi Source/Drain Damage Mitigation with Inner Spacer and Buffer Optimization in Stacked Nanosheet Gate-All-Around Transistors
- - Curtis Durfee
  - Ivo Otto
  - et al.
- 2023
- SSDM 2023
Advanced BEOL Materials, Processes, and Integration to Reduce Line Resistance of Damascene Cu, Co, and Subtractive Ru Interconnects
- - Takeshi Nogami
  - Oleg Gluschenkov
  - et al.
- 2022
- VLSI Technology and Circuits 2022
Etch and Patterning Development for 2nm Node Nanosheet Devices
- - Eric Miller
  - Indira Seshadri
  - et al.
- 2022
- SPIE Advanced Lithography 2022
Review of nanosheet metrology opportunities for technology readiness
- - Mary A. Breton
  - Daniel Schmidt
  - et al.
- 2022
- JM3
EUV single exposure via patterning at aggressive pitch
- - Jing Guo
  - Jennifer Church
  - et al.
- 2021
- SPIE Advanced Lithography 2021

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Patents

- 27 Jan 2020
- US
- 10545409
Dynamic Adjustment Of Post Exposure Bake During Lithography Utilizing Real-time Feedback For Wafer Exposure Delay
- 06 Jan 2020
- US
- 10529569
Self Aligned Pattern Formation Post Spacer Etchback In Tight Pitch Configurations
- 07 Oct 2019
- US
- 10437951
Care Area Generation By Detection Optimized Methodology
- 09 Sep 2019
- US
- 10410875
Alternating Hardmasks For Tight-pitch Line Formation
- 19 Aug 2019
- US
- 10388510
Wet Strippable Opl Using Reversible Uv Crosslinking And De-crosslinking
- 19 Aug 2019
- US
- 10388521
Method To Increase The Lithographic Process Window Of Extreme Ultra Violet Negative Tone Development Resists
- 15 Jul 2019
- US
- 10354922
Simplified Block Patterning With Wet Strippable Hardmask For High Energy Implantation
- 08 Jul 2019
- US
- 10347486
Patterning Material Film Stack With Metal-containing Top Coat For Enhanced Sensitivity In Extreme Ultraviolet (euv) Lithography
- 03 Jun 2019
- US
- 10312103
Alternating Hardmasks For Tight-pitch Line Formation
- 01 Apr 2019
- US
- 10249512
Tunable Tioxny Hardmask For Multilayer Patterning

Blog posts

IBM and Albany partners unlock new yield benchmarks for EUV patterning
Technical note
Luciana Meli and Nelson Felix
24 Oct 2024
- Semiconductors
EUV patterning yield breakthrough sets new benchmark for logic scaling
Technical note
Nelson Felix and Luciana Meli
06 Nov 2020
4 minute read
IBM Research at SPIE 2020: New architectures and fabrications for AI hardware
Research
Nelson Felix
21 Feb 2020
4 minute read
- AI Hardware
- Semiconductors

Top collaborators

Luciana Meli

Senior Manager: Patterning & Metrology

Nicolas Loubet

STSM, Advanced Logic Technology Research

Mary Breton

Technical Assistant to Huiming Bu | Semiconductor Enablement Program Management & Infrastructure

Huiming Bu

Vice President: IBM Semiconductors Global R&D and Albany Operations