Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet TechnologyShogo MochizukiNicolas Loubetet al.2023IEDM 2023
Scaling opportunities for Gate-All-Around and beyond: A patterning perspectiveIndira SeshadriEric Milleret al.2023IEDM 2023
Epi Source/Drain Damage Mitigation with Inner Spacer and Buffer Optimization in Stacked Nanosheet Gate-All-Around TransistorsCurtis DurfeeIvo Ottoet al.2023SSDM 2023
Etch and Patterning Development for 2nm Node Nanosheet DevicesEric MillerIndira Seshadriet al.2022SPIE Advanced Lithography 2022
Nanosheet Metrology Opportunities for Technology ReadinessMary BretonDaniel Schmidtet al.2021SPIE Advanced Lithography 2021
Measuring Local CD Uniformity in EUV vias with scatterometry and machine learningDexin KongDaniel Schmidtet al.2020SPIE Advanced Lithography 2020
Exploration of pillar local CDU improvement options for AI applicationsCharlie LiuHao Tanget al.2020SPIE Advanced Lithography 2020
Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyondCharlie LiuElliott Frankeet al.2018Nature Electronics
19 Aug 2019US10388521Method To Increase The Lithographic Process Window Of Extreme Ultra Violet Negative Tone Development Resists
15 Jul 2019US10354922Simplified Block Patterning With Wet Strippable Hardmask For High Energy Implantation
08 Jul 2019US10347486Patterning Material Film Stack With Metal-containing Top Coat For Enhanced Sensitivity In Extreme Ultraviolet (euv) Lithography
05 Nov 2018US10121661Self Aligned Pattern Formation Post Spacer Etchback In Tight Pitch Configurations
EUV patterning yield breakthrough sets new benchmark for logic scalingTechnical noteNelson Felix and Luciana Meli06 Nov 20204 minute readAI HardwareHardware TechnologyLogic ScalingSemiconductors
IBM Research at SPIE 2020: New architectures and fabrications for AI hardwareResearchNelson Felix21 Feb 20204 minute readAI HardwareSemiconductors