HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing
- R. Khaddam-Aljameh
- M. Stanisavljevic
- et al.
- 2021
- VLSI Technology 2021
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90 results for Pier Andrea Francese
A 25-50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS
- Yang You
- Glen Wiedemeier
- et al.
- 2020
- VLSI Circuits 2020
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET
- Gain Kim
- Lukas Kull
- et al.
- 2019
- A-SSCC 2019
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2018
- VLSI Circuits 2018
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE
- Pier Andrea Francese
- Alessandro Cevrero
- et al.
- 2018
- VLSI Circuits 2018
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration
- Lukas Kull
- Danny Luu
- et al.
- 2018
- VLSI Circuits 2018
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
- Gain Kim
- Lukas Kull
- et al.
- 2018
- ISCAS 2018
DDR4 transmitter with ac-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS Technology
- Marcel Kossel
- Christian Menolfi
- et al.
- 2017
- ESSCIRC 2017
Background calibration using noisy reference ADC for a 12b 600MS/s 2×TI SAR ADC in 14nm CMOS FinFET
- Danny Luu
- Lukas Kull
- et al.
- 2017
- ESSCIRC 2017
A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET
- Alessandro Cevrero
- Ilter Ozkaya
- et al.
- 2017
- VLSI Circuits 2017