Publications

90 results for Pier Andrea Francese

A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration
- - Lukas Kull
  - Danny Luu
  - et al.
- 2018
- VLSI Circuits 2018
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE
- - Pier Andrea Francese
  - Alessandro Cevrero
  - et al.
- 2018
- VLSI Circuits 2018
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders
- - Hazar Yueksel
  - Matthias Braendli
  - et al.
- 2018
- IEEE TCAS-I
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
- - Gain Kim
  - Lukas Kull
  - et al.
- 2018
- ISCAS 2018
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver with Low-Latency Digital CDR in 14-nm CMOS FinFET
- - Ilter Ozkaya
  - Alessandro Cevrero
  - et al.
- 2018
- IEEE JSSC
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS
- - Ilter Ozkaya
  - Alessandro Cevrero
  - et al.
- 2018
- ISSCC 2018
A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS
- - Christian Menoifi
  - Matthias Braendli
  - et al.
- 2018
- ISSCC 2018
A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET
- - Lukas Kull
  - Danny Luu
  - et al.
- 2018
- ISSCC 2018
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels
- - Cosimo Aprile
  - Alessandro Cevrero
  - et al.
- 2018
- IEEE JSSC
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET
- - Ilter Ozkaya
  - Alessandro Cevrero
  - et al.
- 2017
- IEEE JSSC