A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver with Low-Latency Digital CDR in 14-nm CMOS FinFET

Abstract

This paper presents an analysis on the loop dynamics of the digital clock and data recovery (CDR) circuits and the design details of a non-return to zero optical receiver (RX) in a 14-nm bulk CMOS finFET technology with high jitter tolerance (JTOL) performance, which is designed based on the analysis. The digital CDR logic is designed full custom in order to keep it running at a quarter rate clock of 15 GHz at 60-Gb/s sampling speed to minimize the CDR loop latency. The RX is characterized in a vertical cavity surface emitting laser-based link recovering a 7-bit pseudo-random bit sequence bit pattern at 60 Gb/s with a JTOL corner frequency of around 80 MHz while maintaining an energy efficiency of 1.9 pJ/bit.