Lukas Kull, Danny Luu, et al.
ISSCC 2017
The ongoing demand for higher data rates in wireline and optical communications has led to emerging standards in the 100Gb/s+ regime [1]. Although these standards are still in the definition phase they will rely on multi-level signaling such as PAM-4 along with an increasing amount of digital signal processing. In the foreseeable future, a high-performance TX will consist of a CMOS DSP frontend followed by a high sampling rate data converter [2,3], whose design remains a significant challenge. This paper presents a 112Gb/s PAM-4 SST Tx that is based on a quarter-rate 56GS/s 8b SST DAC along with a digital 8-tap FIR filter for channel equalization.
Lukas Kull, Danny Luu, et al.
ISSCC 2017
Alessandro Cevrero, Ilter Ozkaya, et al.
ISSCC 2019
Ilter Ozkaya, Alessandro Cevrero, et al.
IEEE JSSC
Marcel Kossel, Christian Menolfi, et al.
ESSCIRC 2017