Optical communication standards, such as ITU OTU-4, OIF 112G and 100/400Gb/s Ethernet, require ADCs with more than 50GS/s and at least 5 ENOB to enable complex digital equalization, and a growing number of appropriate designs have been presented [1-4], mostly time-interleaved SAR ADCs. Most of these ADCs were not intended for input frequencies up to Nyquist and report an input range up to approximately 20GHz, often equivalent to the analog 3dB bandwidth. Ultimately, the analog bandwidth is less relevant than SNDR at high frequencies because an FIR filter can equalize amplitude degradation, but not increase SNDR. The design presented in this paper does not focus on the 3dB bandwidth, but it is optimized for best SNDR at the Nyquist frequency of up to 36GHz. Low power and area are critical for many applications and are achieved by an optimized SAR that allows low supply voltages while still maintaining high speed and accuracy. At 72GS/s, the ADC achieves 39.3dB at low input frequencies and 30.4dB at Nyquist. It consumes 235mW at 72GS/s and 97mW at 48GS/s, which results in 3.3pJ and 2.0pJ per conversion, respectively. The ADC is implemented in an area of 0.15mm2 in 14nm CMOS FinFET technology.