Publication
VLSI Circuits 2018
Conference paper

A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration

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Abstract

An asynchronous 48× interleaved SAR ADC optimized for high SNDR above 20 GHz input frequency operating at 20-40 GS/s is presented. The ADC features an 8-channel interleaver with clock demultiplexing for enhanced bandwidth, a power- and area-optimized 2-stage SAR ADC, and bandwidth adjustment in the input sampling path. At 32 GS/s and 199 mW power consumption it achieves 47.3 dB SNDR near DC and 37.8 dB at 40 GHz input frequency with a core chip area of 0.16 mm2 in 14 nm FinFET CMOS technology.

Date

22 Oct 2018

Publication

VLSI Circuits 2018

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