Publication
VLSI Circuits 2018
Conference paper

A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE

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Abstract

A decision feedback equalization (DFE) technique suitable for high data-rate I/O link receivers is presented. The technique leverages quarter-rate data slicing to implement a fully speculative 3-tap DFE and uses clock forwarding to reach a speed of 50Gb/s. It corresponds to 20ps timing closure of the most critical path, which is the feedback of the first DFE tap. The RX data-path is implemented in 14nm FinFET CMOS SOI technology. At 0.9V supply the energy-efficiency is 1.6pJ/b when PRBS15 data transmitted at 50Gb/s across a channel with 32.5dB insertion loss are recovered with >30% horizontal margin (BER<10-12).

Date

22 Oct 2018

Publication

VLSI Circuits 2018

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