Publications

This is our catalog of recent publications authored by IBM researchers, in collaboration with the global research community. We’re currently adding our back catalog of more than 110,000 publications. It’s an ever-growing body of work that shows why IBM is one of the most important contributors to modern computing.

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58 results for Pier Andrea Francese

An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOS
- - Marcel Kossel
  - Vishal Khatri
  - et al.
- 2021
- ISSCC 2021
An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with 2× Interpolating Sense-Amplifier-Latches
- - Abdullah Serdar Yonar
  - Pier Andrea Francese
  - et al.
- 2023
- ISSCC 2023
HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing
- - Riduan Khaddam Aljameh
  - Milos Stanisavljevic
  - et al.
- 2021
- VLSI Technology 2021
HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing
- - Riduan Khaddam-Aljameh
  - Milos Stanisavljevic
  - et al.
- 2021
- VLSI Circuits 2021
A 25-50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS
- - Yang You
  - Glen Wiedemeier
  - et al.
- 2020
- VLSI Circuits 2020
30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET
- - Gain Kim
  - Lukas Kull
  - et al.
- 2019
- ISSCC 2019
6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET
- - Alessandro Cevrero
  - Ilter Ozkaya
  - et al.
- 2019
- ISSCC 2019
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS
- - Thomas Toifl
  - Christian Menolfi
  - et al.
- 2018
- VLSI Circuits 2018
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE
- - Pier Andrea Francese
  - Alessandro Cevrero
  - et al.
- 2018
- VLSI Circuits 2018
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration
- - Lukas Kull
  - Danny Luu
  - et al.
- 2018
- VLSI Circuits 2018