A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET
- Jaewon Lee
- Pier Andrea Francese
- et al.
- 2025
- ISSCC 2025
Publications
90 results for Pier Andrea Francese
A DAC-Based Discrete Multitone Wireline Transmitter in 5nm FinFET
- Seoyoung Jang
- Marcel Kossel
- et al.
- 2025
- ISSCC 2025
A 40 GS/s 8b-DAC SST-TX in 7 nm FinFET CMOS for cryogenic quantum applications with 32kB SRAMbased RF-DDS AWG
- Marcel Kossel
- Matthias Brandli
- et al.
- 2024
- ESSERC 2024
A NRZ/PAM4 SST TX in 5nm FinFET CMOS with 3-tap FFE and 0.7pJ/b efficiency at 100 Gb/s PAM4
- Marcel Kossel
- Matthias Brandli
- et al.
- 2024
- ESSERC 2024
A 40 GS/s 8b-DAC SST-TX in 7 nm FinFET CMOS for cryogenic quantum applications with 32kB SRAM-based RF-DDS AWG
- 2024
- ESSERC 2024
A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- ISCAS 2024
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration
- Tod Dickson
- Zeynep Toprak Deniz
- et al.
- 2024
- CICC 2024
A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- IEEE TCAS-II
A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers
- Donggeon Kim
- Yujin Choi
- et al.
- 2024
- IEEE TCAS-I
A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- IEEE TCAS-II