Publication
VLSI Technology 2019
Conference paper

Technology challenges and enablers to extend Cu metallization to beyond 7 nm node

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Abstract

Electromigration (EM) and TDDB reliability of Cu interconnects with a barrier/wetting layer as thin as 2 nm employing a PVD-reflowed through-Co self-forming barrier (tCoSFB) is demonstrated to meet the required specifications for 7 nm BEOL. The resulting Cu EM lifetime is 2000X longer than Cu interconnects with a standard scaled barrier/wetting layer. This tCoSFB Cu EM and TDDB reliability performance were equivalent to pure Co metal interconnects, but with a 50% lower line resistance even down to 30 nm pitch dimensions. However, the annealing process for PVD-reflow Cu seed that enhances EM reliability caused Cu agglomeration at dual damascene line-end vias, leading to poor via-chain yield. Resolving this geometry-sensitive via-fill problem was identified as key to extending Cu manufacturability to 7 nm and beyond. We propose, and show preliminary data, for Cu/tCoSFB metallization with CVD Co via pre-fill as potential solution.

Date

01 Jun 2019

Publication

VLSI Technology 2019

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