A 14 nm embedded STT-MRAM CMOS technology
- Daniel C. Edelstein
- M. Rizzolo
- et al.
- 2020
- IEDM 2020
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56 results for Son Van Nguyen
Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- C. J. Penny
- Koichi Motoyama
- et al.
- 2022
- IEDM 2022
Advanced BEOL Materials, Processes, and Integration to Reduce Line Resistance of Damascene Cu, Co, and Subtractive Ru Interconnects
- Takeshi Nogami
- Oleg Gluschenkov
- et al.
- 2022
- VLSI Technology and Circuits 2022
Electromigration and Line R of Graphene Capped Cu Dual Damascene Interconnect
- T. Nogami
- S. Nguyen
- et al.
- 2021
- IEDM 2021
Fully aligned via integration for extendibility of interconnects to beyond the 7 nm node
- Benjamin D. Briggs
- C.B. Peethala
- et al.
- 2017
- IEDM 2017
Air spacer for 10nm FinFET CMOS and beyond
- K. Cheng
- C. Park
- et al.
- 2016
- IEDM 2016
Through-Cobalt Self Forming Barrier (tCoSFB) for Cu/ULK BEOL: A novel concept for advanced technology nodes
- Takeshi Nogami
- Benjamin D. Briggs
- et al.
- 2015
- IEDM 2015
High reliability 32 nm Cu/ULK BEOL based on PVD CuMn seed, and its extendibility
- Takeshi Nogami
- Tibor Bolom
- et al.
- 2010
- IEDM 2010
Reactive Vapor-Phase Inhibitors for Area-Selective Depositions at Tunable Critical Dimensions
- Lawal Adewale Ogunfowora
- Ishwar Singh
- et al.
- 2024
- JACS
Resistive Memory Process Optimization for High Resistance Switching Toward Scalable Analog Compute Technology for Deep Learning
- Youngseok Kim
- Soon-Cheon Seo
- et al.
- 2021
- IEEE Electron Device Letters