Publications

63 results for Dechao Guo

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- - S. Krishnan
  - U. Kwon
  - et al.
- 2011
- IEDM 2011
Critical analysis of 14nm device options
- - Phil Oldiges
  - R. Muralidhar
  - et al.
- 2011
- SISPAD 2011
Characterization of parasitic bipolar transistors in 45 nm silicon-on-insulator technology
- - Larry Wissel
  - Phil Oldiges
  - et al.
- 2010
- IEEE TNS
Wafer scale fabrication of carbon nanotube FETs with embedded poly-gates
- - Shu-Jen Han
  - Josephine Chang
  - et al.
- 2010
- IEDM 2010
Stress liner proximity technique to enhance carrier mobility in high-κ metal gate MOSFETs
- - Dechao Guo
  - Kathryn Schonenberg
  - et al.
- 2009
- MRS Fall Meeting 2009
Intrinsic effective mobility extraction with extremely scaled gate dielectrics
- - Zuoguang Liu
  - Dechao Guo
  - et al.
- 2010
- Applied Physics Letters
Reverse temperature dependence of circuit performance in high- k/metal-gate technology
- - Shu-Jen Han
  - Dechao Guo
  - et al.
- 2009
- IEEE Electron Device Letters
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm ² SRAM and ultra low-k back end with eleven levels of copper
- - B. Greene
  - Q. Liang
  - et al.
- 2009
- VLSI Technology 2009
Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate
- - K. Henson
  - H. Bu
  - et al.
- 2008
- IEDM 2008
On the difference of temperature dependence of metal gate and poly gate SOI MOSFET threshold voltages
- - Shu-Jen Han
  - Xinlin Wang
  - et al.
- 2008
- IEDM 2008