IEDM 2008
Conference paper

Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

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CMOS devices with high- k / metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630μA/μm and 1190μA/μm have been demonstrated in 45nm groundrules at 1V and 200nA/μm off current for nFETs and pFETs, at a Tinv of 14Å and 15Å respectively. The drive currents were achieved using a simplified high- k / metal gate integration scheme with embedded SiGe and dual stress liners (DSL) and without utilizing additional stress enhancers. Devices have been fabricated with Tinv's down to 12Å and 10.5Å demonstrating the scalability of this approach for 32nm and beyond.