One critical factor that determines the feasibility of employing carbon nanotubes as channel materials for post-silicon logic devices is the process compatibility to the current CMOS process flow. We show a wafer-scale integration scheme of carbon nanotube field-effect transistor (CNFET) that is performed by 8″ production tools. High density CNT arrays were transferred on the processed wafer, and high performance CNFET with an excellent subthreshold slope (88 mV /decade) is demonstrated. We further show that the work-function tuning enabled by the conventional gate doping can be achieved in our novel embedded poly-Si gate structure. Approximate Vt change of 0.6V, from n-gate to p-gate, is observed. The Vt shift being smaller than the gate work function difference can be attributed to the Fermi level pinning between poly-Si and high-k interface. ©2010 IEEE.