Publications

63 results for Dechao Guo

Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- - J. Zhang
  - S. Pancharatnam
  - et al.
- 2019
- IEDM 2019
Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications
- - Ruqiang Bao
  - Reinaldo A. Vega
  - et al.
- 2019
- IEDM 2019
Yield learning methodologies and failure isolation in ring oscillator circuit for CMOS technology research
- - Victor Chan
  - Kangguo Cheng
  - et al.
- 2019
- IEEE Trans Semicond Manuf
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- - A. Greene
  - Huimei Zhou
  - et al.
- 2019
- VLSI Technology 2019
Direct Partition Measurement of Parasitic Resistance Components in Advanced Transistor Architectures
- - Zuoguang Liu
  - Heng Wu
  - et al.
- 2019
- VLSI Technology 2019
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- - Ruilong Xie
  - Chanro Park
  - et al.
- 2019
- VLSI Technology 2019
Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor
- - Miaomiao Wang
  - Jingyun Zhang
  - et al.
- 2019
- IRPS 2019
Failure isolation in ring oscillator circuit and defect detection in CMOS technology research
- - Victor Chan
  - M. Bergendahl
  - et al.
- 2019
- ASMC 2019
Extendable and Manufacturable Volume-less Multi-Vt Solution for 7nm Technology Node and beyond
- - Ruqiang Bao
  - Huimei Zhou
  - et al.
- 2018
- IEDM 2018
Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- - Heng Wu
  - Oleg Gluschenkov
  - et al.
- 2018
- IEDM 2018