About cookies on this site Our websites require some cookies to function properly (required). In addition, other cookies may be used with your consent to analyze site usage, improve the user experience and for advertising. For more information, please review your options. By visiting our website, you agree to our processing of information as described in IBM’sprivacy statement. To provide a smooth navigation, your cookie preferences will be shared across the IBM web domains listed here.
Publication
IRPS 2019
Conference paper
Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor
Abstract
In this paper, we report the bias temperature instability (BTI) reliability in stacked gate-all-around (GAA) nanosheet (NS) devices. We show that, in addition to its superior intrinsic performance over FinFET and stacked nanowire (NW), stacked NS can also provide NBTI reliability benefit, owing to domination of (100) surface conduction and mitigation of field enhancement effect in ultra-scaled GAA structure.