A fully aligned via (FAV) integration scheme is introduced and demonstrated at 36 nm metal pitch, with extendibility to beyond the 7 nm node. Selective chemistries were developed to recess Cu and W wires and their associated barrier liner materials, so as to create local topography with no adverse effects on these wiring levels or their dielectrics. Dielectric cap layers were optimized for excellent via RIE selectivity, to act as via guiding structures during subsequent level pattern definition. This combination mitigates via overlay and critical dimension (CD) errors. FAV integration can enable line/via area scaling for 70% lower line resistances and 30% larger via contact areas at the same node. Concurrently, FAV improves TDDB reliability through increased minimum insulator spacing, and EM reliability by maximizing via/wire contact area.