A 40 GS/s 8b-DAC SST-TX in 7 nm FinFET CMOS for cryogenic quantum applications with 32kB SRAM-based RF-DDS AWG
- 2024
- ESSERC 2024
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90 results for Pier Andrea Francese
A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers
- Donggeon Kim
- Yujin Choi
- et al.
- 2024
- IEEE TCAS-I
Experimental efficiency evaluation of stacked transistor half-bridge topologies in 14 nm cmos technology
- Pedro André Martins Bezerra
- Florian Krismer
- et al.
- 2021
- Electronics (Switzerland)
An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier with a Precision That Scales Linearly in Area, Time, and Power
- Riduan Khaddam-Aljameh
- Pier Andrea Francese
- et al.
- 2021
- IEEE Transactions on VLSI Systems
A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- IEEE TCAS-II
A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- IEEE TCAS-II
A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- IEEE TCAS-II
Design of synchronous frequency dividers in 5-nm FinFET CMOS technology
- 2023
- Electronics Letters
Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology
- Sandro Widmer
- Marcel Kossel
- et al.
- 2023
- IEEE TCAS-II
An 8b 1.0-to-1.25 GS/s Time-Based ADC With Bipolar VTC and Sense Amplifier Latch Interpolated Gated Ring Oscillator TDC
- A. Serdar Yonar
- Pier Andrea Francese
- et al.
- 2023
- IEEE SSC-L