Design of synchronous frequency dividers in 5-nm FinFET CMOS technology
- 2023
- Electronics Letters
Publications
Patents
- 26 Feb 2024
- US
- 11916568
- 13 Nov 2023
- US
- 11816062
- 06 Nov 2023
- US
- 11811418
- 15 May 2023
- US
- 11652493
- 11 May 2023
- CN
- ZL201880035590.8
- 03 Apr 2023
- US
- 11621720
- 06 Apr 2022
- JP
- 7055154
- 15 Mar 2022
- GB
- 2576666
- 07 Mar 2022
- US
- 11271550
- 20 Dec 2021
- US
- 11205131
Projects
High-Speed I/O Links
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.
Top collaborators
PF
Pier Andrea Francese
Principal RSM - Analog Circuit Design
MB
Matthias Brändli
Digital Circuit Design
TM
Thomas Morf
Senior Research Scientist