Digital SNN in 5 nm FinFET CMOS with latency-reducing hybrid spiking scheme operated at 2.6 GHz
- Marcel Kossel
- Giovanni Cherubini
- et al.
- 2025
- ICM 2025
Marcel Kossel
Title
Circuit Designer
Bio
Education:
- 1997: MSEE ETHZ
- 2000: PhD EE ETHZ
- 2001: NDS EE ETHZ
Job Title: Senior Research Scientist, 2022
Memberships: IEEE Senior Member, 2009
Research Activities: Integrated Circuit Design (analog, mixed-signal)
Research Areas:
- Wireline communication, high-speed interconnect technology
- High-speed data converters and equalizers
- Hardware implementation of neural networks
- Control electronics for quantum computing
Papers: 90+ (status 2024)
Patents: 50+ (status 2024)
Publications
A DAC-Based Discrete Multitone Wireline Transmitter in 5nm FinFET
- Seoyoung Jang
- Marcel Kossel
- et al.
- 2025
- ISSCC 2025
A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- ISCAS 2024
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration
- Tod Dickson
- Zeynep Toprak Deniz
- et al.
- 2024
- CICC 2024
Design of synchronous frequency dividers in 5-nm FinFET CMOS technology
- 2023
- Electronics Letters
Patents
- US
- 12278598
- US
- 12095473
- US
- 12088316
- US
- 12088314
- TW
- I851057
- TW
- I850965
- US
- 11916568
- US
- 11816062
- US
- 11811418
- US
- 11652493
Projects
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.
Top collaborators
PF
Pier Andrea Francese
Principal RSM - Analog Circuit Design
MB
Matthias Brändli
Digital Circuit Design
SW
Stanislaw Wozniak
Staff Research Scientist
AP
Angeliki Pantazi
Principal Research Scientist, Manager AI Platform