An 8b 1.0-to-1.25 GS/s Time-Based ADC With Bipolar VTC and Sense Amplifier Latch Interpolated Gated Ring Oscillator TDC
- Abdullah Serdar Yonar
- Pier Andrea Francese
- et al.
- 2023
- IEEE SSC-L
Publications
Design of Time-Encoded Spiking Neural Networks in 7nm CMOS Technology
- Sandro Widmer
- Marcel Kossel
- et al.
- 2023
- IEEE TCAS-II
An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with 2× Interpolating Sense-Amplifier-Latches
- Abdullah Serdar Yonar
- Pier Andrea Francese
- et al.
- 2023
- ISSCC 2023
Patents
Successive-approximation Analog-to-digital Converters
- 15 May 2023
- US
- 11652493
Sequence Detection
- 11 May 2023
- CN
- ZL201880035590.8
Quantum Processing Apparatus With Downsampling Analog-to-digital Converter
- 03 Apr 2023
- US
- 11621720
Sequence Detection
- 06 Apr 2022
- JP
- 7055154
Sequence Detection
- 15 Mar 2022
- GB
- 2576666
Synchronous Divider Based On Cascaded Retiming
- 07 Mar 2022
- US
- 11271550
Sequence Detection
- 20 Dec 2021
- US
- 11205131
Operating A Wireline Receiver With A Tunable Timing Characteristic
- 16 Aug 2021
- US
- 11095487
Clock Divider With Quadrature Error Correction
- 05 Jul 2021
- US
- 11057039
Memory Receiver With Resistive Voltage Divider
- 08 Mar 2021
- US
- 10943653
Projects
High-Speed I/O Links
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.
Top collaborators
PF
Pier Andrea Francese
Principal RSM - Analog Circuit Design
MB
Matthias Brändli
Digital Circuit Design
MP
Mridula Prathapan
Quantum control theory and hardware design
TM
Thomas Morf
Senior Research Scientist