Publication
IEEE SSC-L
Paper

An In-Comparator Aperture-Time Equalization in a 7-nm FinFET CMOS 40-Gb/s Receiver

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Abstract

This letter proposes an in-comparator aperture-time equalization scheme using the impulse response of a clocked comparator. The technique is applied in a wireline link receiver prototype, implemented in CMOS 7-nm FinFET technology. The proposed method controls the aperture properties of the slicers by shaping their impulse sensitivity functions. We demonstrate an aperture skew control range of 4.7 ps with 147-fs accuracy for NRZ signaling at 40 Gb/s. PAM4 signaling at 80 Gb/s is also showcased using the proposed technique. These results serve as a proof of concept for next-generation source-synchronous chip-to-chip dense I/O links where aperture-time skews could be fine adjusted inside each comparator.

Date

01 Jan 2020

Publication

IEEE SSC-L

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