A NRZ/PAM4 SST TX in 5nm FinFET CMOS with 3-tap FFE and 0.7pJ/b efficiency at 100 Gb/s PAM4

Abstract

A source-series terminated (SST) transmitter (TX) for NRZ and PAM4 signaling across short reach channels (e.g., from a hub-chip to a processor die) is presented. The TX operates up to 100 Gb/s PAM4 and shows an efficiency of 0.7 pJ/b running from a 0.8 V supply. It provides feed-forward equalization (FFE) with 3 taps. There are 48 output stages of which 33 are assigned to the main tap and 15 are configurable to act as either pre-cursor, main or post-cursor taps. The target impedance of 50Ω is obtained at nominal conditions with 44 enabled output stages. This results in a maximum de-emphasis level of approximately 6 dB (33 main tap weights, 11 FFE tap weights). The TX is operated with a half-rate clock and provides in its clock path quadrature-error correction (QEC) and duty cycle error correction (DCC). The data path has a 32:1 serialization factor. The TX is fabricated in 5 nm FinFET CMOS technology and occupies an area of 220μ m×90μ m.