Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration

Abstract

DAC-based wireline transmitters are a critical component of wireline electrical links operating above 100 Gb/s. As systems explore the use of more sophisticated modulation formats such as higher-order time domain pulse amplitude modulation (e.g., PAM6 or PAM8) or frequency domain modulation (e.g., OFDM), higher linearity DACs will be required than those employed in existing PAM4 systems. This paper explores wireline DAC design. Tradeoffs between current-mode and voltage-mode (SST) drivers are described. Two design examples are presented as case studies. The first describes a CML-based 8b 56-GS/s DAC in 7nm FinFET which includes a novel integrated linearity calibration technique. The design achieves nearly 1Vppd output swing and 1.1 pJ/bit energy efficiency for 112Gb/s PAM4 signaling. The second design describes an 8b 72-GS/s DAC in 4nm FinFET with SST driver, achieving excellent static linearity to support high-order time and frequency domain modulation for future communication links.