This work provides the first experimental demonstration of data scrubbing effectiveness for MRAM, using an 80 Mb array with 40 nm critical dimension (CD). We demonstrate improved endurance without chip error rate (CER) penalty for last level cache (LLC) applications. An analytical model is built to understand the 10 year chip error rate dependence on data scrubbing frequency, error correction code (ECC) strength, and data retention energy barrier (Eb). A low Eb MTJ stack is then compared to the process of record (POR) stack for data scrubbing at 85 C, showing 20% Eb and 15% switching current reduction without degrading CER with 5 s scrubbing. Finally, an ultra-low Eb stack is explored, delivering 30% Eb reduction and 2 orders of magnitude higher endurance without CER penalty by using 1 s scrubbing. This work points out the great potential of MRAM for LLC applications with data scrubbing.