Control of Plasma Etch Conditions through Pulsed, Cyclic, and QALE Processes for Advanced Node ApplicationsDominik Metzler2023PESM 2023
Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect ScalingChris PennyKoichi Motoyamaet al.2022IEDM 2022
Etch and Patterning Development for 2nm Node Nanosheet DevicesEric MillerIndira Seshadriet al.2022SPIE Advanced Lithography 2022
First Experimental Demonstration of MRAM Data Scrubbing: 80 Mb MRAM with 40 nm junctions for Last Level Cache ApplicationsHeng WuVeenadhar Katragaddaet al.2021IEDM 2021
Significance of plasma-photoresist interactions for atomic layer etching processes with extreme ultraviolet photoresistAdam PrandaKang Yi Linet al.2020JVSTA
Selective atomic layer etching of HfO2 over silicon by precursor and substrate-dependent selective depositionKang Yi LinChen Liet al.2020JVSTA
Simulation of photoresist defect transfer through subsequent patterning processesDominik MetzlerMohamed Oulmaneet al.2020SPIE Advanced Lithography 2020
Exploration of pillar local CDU improvement options for AI applicationsCharlie LiuHao Tanget al.2020SPIE Advanced Lithography 2020
An evaluation of Fuchs-Sondheimer and Mayadas-Shatzkes models below 14nm node wide linesR. S. SmithE. T. Ryanet al.2019AIP Advances
Achieving ultrahigh etching selectivity of SiO2 over Si3N4 and Si in atomic layer etching by exploiting chemistry of complex hydrofluorocarbon precursorsKang Yi LinChen Liet al.2018JVSTA
Method For Fabricating A Semiconductor Device Including Self-aligned Top Via Formation At Line Ends01 Aug 2022US11404317
Placing Top Vias At Line Ends By Selective Growth Of Via Mask From Line Cut Dielectric29 Nov 2021US11189561