In this paper, we demonstrate a novel Source Drain Extension (SDE) approach to enable NMOS device scaling along with improved performance. For the first time, SDE formation with epitaxially grown As doped Si (Si:As) has been examined and compared to the current state-of-the-art SDE formation in FinFET at 10nm logic ground rules. It is found that a Si:As layer based SDE provides a clear improvement in the short channel effect and a significant device performance increase. It is also shown that a careful co-optimization of the Si:As layer and Source / Drain (S/D) lateral recess is required to achieve the optimum device gain. This paves the way for the ultimate nSDE formation for current and next generation CMOS devices.