IEEE Journal of Solid-State Circuits

A 45 nm SOI embedded DRAM macro for the POWER™ processor 32 MByte on-chip L3 cache

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A 1.35 ns random access and 1.7 ns-random-cycle SOI embedded-DRAM macro has been developed for the POWER7™ high-performance microprocessor. The macro employs a 6 transistor micro sense-amplifier architecture with extended precharge scheme to enhance the sensing margin for product quality. The detailed study shows a 67% bit-line power reduction with only 1.7% area overhead, while improving a read zero margin by more than 500ps. The array voltage window is improved by the programmable BL voltage generator, allowing the embedded DRAM to operate reliably without constraining of the microprocessor voltage supply windows. The 2.5nm gate oxide (GOX) transistor cell with deep-trench capacitor is accessed by the 1.7 V wordline high voltage (VPP) with -0.4 V WL low voltage (VWL), and both are generated internally within the microprocessor. This results in a 32 MB on-chip L3 on-chip-cache for 8 cores in a 567 mm 2 POWER7™ die. © 2006 IEEE.