Isolated Preset Architecture for a 32nm SOI embedded DRAM macro
John Barth, Don Plass, et al.
VLSI Circuits 2012
We describe a single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation , a 4 Kb one-time-programmable read-only memory ( OTPROM ) for redundancy and repair control, on-chip OTPROM programming voltage generation, clock generation and distribution, array built-in self-test circuitry (ABIST), user logic and pervasive logic. The eDRAM employs a programmable pipeline, achieving 1.8 ns latency, and features concurrent refresh capability. © 2006 IEEE.
John Barth, Don Plass, et al.
VLSI Circuits 2012
Peter Klim, John Barth, et al.
VLSI Circuits 2008
John Barth, William R. Reohr, et al.
IEEE Journal of Solid-State Circuits
Philip G. Emma, William R. Reohr, et al.
IEEE Micro