A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- John Barth
- William Reohr
- et al.
- 2007
- ISSCC 2007
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15 results for W. Reohr
Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5Ghz
- S.E. Schuster
- W. Reohr
- et al.
- 2000
- ISSCC 2000
A 10ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell
- R. Scheuerlein
- W.J. Gallagher
- et al.
- 2000
- ISSCC 2000
Statistical yield analysis of silicon-on-insulator embedded DRAM
- R. Kanj
- R.V. Joshi
- et al.
- 2009
- ISQED 2009
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM
- J.B. Kuang
- A. Mathews
- et al.
- 2008
- ESSCIRC 2008
A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
- Peter Klim
- John Barth
- et al.
- 2008
- VLSI Circuits 2008
Memories: Exploiting them and developing them
- William Robert Reohr
- 2006
- SOCC 2006
A High-Speed 128Kbit MRAM Core for Future Universal Memory Applications
- A. Bette
- J.K. DeBrosse
- et al.
- 2003
- VLSI Circuits 2003
Ratioed CMOS: A low power high speed design choice in SOI technologies
- Christophe R. Tretz
- Robert K. Montoye
- et al.
- 2000
- IEEE International SOI Conference 2000
A 45 nm SOI embedded DRAM macro for the POWER™ processor 32 MByte on-chip L3 cache
- John Barth
- Don Plass
- et al.
- 2011
- IEEE Journal of Solid-State Circuits