A 45 nm SOI embedded DRAM macro for the POWER™ processor 32 MByte on-chip L3 cache
- John Barth
- Don Plass
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
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Power-constrained high-frequency circuits for the IBM POWER6 microprocessor
- Brian Curran
- Eric Fluhr
- et al.
- 2007
- IBM J. Res. Dev