IBM POWER7 processor circuit design

The IBM POWER7® processor contains many innovative circuit ideas that enable advanced architectural features. A high-density embedded dynamic random access memory is used to provide 32 MB of level-3 cache. Improved input/output (I/O) links provide up to 50 GB/s of I/O bandwidth. An innovative phase-locked loop design allows for dynamic, per-core frequency variation, and unique multiport techniques for register files as well as six-transistor cell-based memory cells to support the superscalar multithreaded out-of-order processor. © 2011 by International Business Machines Corporation.