A 0.6 µm² 256Mb Trench DRAM Cell with Self-Aligned Buried Strap (BEST)

Abstract

In order to realize a small cell and a simple process for a 256 Mbit DRAM, a trench cell with the unique feature of a self-aligned BuriEd STrap (BEST) is proposed. This and other process features result in a folded bitline cell with an area of 0.605 µm2 at 0.25 µm design rules, which is the smallest of the proposed 256 Mb DRAM conventional folded bitline cells (1-3). The BEST cell concept, process, and design, as well as preliminary results obtained from a 256Mb DRAM development test chip, processed with optical lithography down to 0.25 µm design rules, are presented in this paper.