A 0.6 µm2 256Mb Trench DRAM Cell with Self-Aligned Buried Strap (BEST)
- L.A. Nesbit
- J. Alsmeier
- et al.
- 1993
- IEDM 1993
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4 results for Stephen A. Parke
Fault-tolerant designs for 256 Mb DRAM
- Toshiaki Kirihata
- Yohji Watanabe
- et al.
- 1996
- IEEE Journal of Solid-State Circuits
Fault-tolerant designs for 256 Mb DRAM
- Toshiaki Kirihata
- Yohji Watanabe
- et al.
- 1996
- IEICE Transactions on Electronics
Highspeed Sensing Scheme for CMOS DRAM's
- Sang H. Dhong
- Nicky Chau-Chun Lu
- et al.
- 1988
- IEEE Journal of Solid-State Circuits