A 14 nm embedded STT-MRAM CMOS technology
- Daniel C. Edelstein
- M. Rizzolo
- et al.
- 2020
- IEDM 2020
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24 results for J. DeBrosse
A statistical study of magnetic tunnel junctions for high-density spin torque transfer-MRAM (STT-MRAM)
- R. Beach
- T. Min
- et al.
- 2008
- IEDM 2008
220 mm2 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture
- T. Kirihata
- M. Gall
- et al.
- 1998
- ISSCC 1998
A 0.6 µm2 256Mb Trench DRAM Cell with Self-Aligned Buried Strap (BEST)
- L.A. Nesbit
- J. Alsmeier
- et al.
- 1993
- IEDM 1993
A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)
- B. Davari
- C. Koburger
- et al.
- 1989
- IEDM 1989
A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing
- J. DeBrosse
- T. Maffitt
- et al.
- 2015
- CICC 2015
Recent advances in MRAM technology
- W.J. Gallagher
- D.W. Abraham
- et al.
- 2005
- VLSI Technology 2005
A 16Mb MRAM featuring bootstrapped write drivers
- J.K. DeBrosse
- C. Arndt
- et al.
- 2004
- VLSI Circuits 2004
A High-Speed 128Kbit MRAM Core for Future Universal Memory Applications
- A. Bette
- J.K. DeBrosse
- et al.
- 2003
- VLSI Circuits 2003
0.21 μm2 7F2 trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM
- C. Radens
- U. Gruening
- et al.
- 1998
- VLSI Technology 1998