High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005
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23 results for Gary Bronner
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
Trade-offs in the integration of high performance devices with trench capacitor DRAM
- S.W. Crowder
- S. Stiffler
- et al.
- 1997
- IEDM 1997
A 0.6 µm2 256Mb Trench DRAM Cell with Self-Aligned Buried Strap (BEST)
- L.A. Nesbit
- J. Alsmeier
- et al.
- 1993
- IEDM 1993
Trench storage capacitors for high density DRAMs
- T.V. Rajeevakumar
- T. Lii
- et al.
- 1991
- IEDM 1991
Fabrication of CMOS on ultrathin SOI obtained by epitaxial lateral overgrowth and chemical-mechanical polishing
- G. Shahidi
- B. Davari
- et al.
- 1990
- IEDM 1990
Buried-trench DRAM cell using a self-aligned epitaxy over trench technology
- N.C.-C. Lu
- T.V. Rajeevakumar
- et al.
- 1988
- IEDM 1988
Vertically self-aligned buried junction formation for ultrahigh-density DRAM applications
- J. Beintner
- Y. Li
- et al.
- 2004
- IEEE Electron Device Letters
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
On the retention time distribution of dual-channel vertical DRAM technologies
- J. Beintner
- Y. Li
- et al.
- 2003
- VLSI-TSA 2003