Huiming Bu

Overview

Title

Vice President: IBM Semiconductors Global R&D and Albany Operations

Location

IBM Research - Albany Albany, NY USA

Bio

Dr. Huiming Bu is responsible for IBM global Semiconductor R&D strategy across world-wide labs. He oversees R&D activities in advanced logic, chiplet and advanced packaging, emerging memory and analog AI hardware at IBM Research. In addition to leading semiconductor technology R&D agenda, Huiming is also responsible for IBM Research Albany Lab site and fab operations.

Huiming has ~20 years of professional experience in semiconductor technology R&D at IBM after he received his Ph.D. in Electrical Engineering from Yale University. Huiming has authored/co-authored 100+ technical publications and holds 100+ patents in semiconductor domain.

Huiming started his technical career at IBM on High-κ/Metal Gate project and then led SOI FinFET research and early development for IBM’s 14nm node technology. After that, Huiming and his team delivered 10nm/7nm technology R&D for IBM and its Joint Development Alliance (JDA) partners. They are now working on 2nm development and 1nm & beyond pathfinding R&D. Recently, as IBM formed Semiconductors division under IBM Research, the footprint has expanded from advanced logic to chiplet & advanced packaging, intelligent fab, cloud based EDA and design.

Publications

Challenges and Opportunities for Stacked Transistor: DTCO and Device
- - J. Wang
  - S.D. Suk
  - et al.
- 2021
- VLSI Technology 2021
Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel
- - Shogo Mochizuki
  - M. Bhuiyan
  - et al.
- 2020
- IEDM 2020
Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
- - Su-Chen Fan
  - Ruilong Xie
  - et al.
- 2020
- IITC 2020
Selective Enablement of Dual Dipoles for near Bandedge Multi-Vt Solution in High Performance FinFET and Nanosheet Technologies
- - Ruqiang Bao
  - K. Watanabe
  - et al.
- 2020
- VLSI Technology 2020
A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices
- - Nicolas Loubet
  - T. Devarajan
  - et al.
- 2019
- IEDM 2019
Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications
- - Ruqiang Bao
  - Reinaldo A. Vega
  - et al.
- 2019
- IEDM 2019
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- - J. Zhang
  - S. Pancharatnam
  - et al.
- 2019
- IEDM 2019
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- - Ruilong Xie
  - Chanro Park
  - et al.
- 2019
- VLSI Technology 2019
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- - A. Greene
  - Huimei Zhou
  - et al.
- 2019
- VLSI Technology 2019
Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor
- - Miaomiao Wang
  - Jingyun Zhang
  - et al.
- 2019
- IRPS 2019

Patents

- 27 Nov 2012
- US
- 8318565
High-k Dielectric Gate Structures Resistant To Oxide Growth At The Dielectric/silicon Substrate Interface And Methods Of Manufacture Thereof
- 16 Oct 2012
- US
- 8288218
Device Structure, Layout And Fabrication Method For Uniaxially Strained Transistors
- 04 Sep 2012
- US
- 8258037
Nanopillar Decoupling Capacitor
- 17 Jan 2012
- US
- 8097520
Integration Of Passive Device Structures With Metal Gate Layers
- 11 Oct 2011
- US
- 8035173
Cmos Transistors With Differential Oxygen Content High-k Dielectrics
- 17 May 2011
- US
- 7943460
High-k Metal Gate Cmos
- 04 Jan 2011
- US
- 7863123
Direct Contact Between High-k/metal Gate And Wiring Process Flow
- 08 Dec 2010
- CN
- ZL200810125977.0
Cmos Transistors With Differential Oxygen Content High-k Dielectrics
- 13 Apr 2010
- US
- 7696036
Cmos Transistors With Differential Oxygen Content High-k Dielectrics

Top collaborators

Huiming Bu

Overview

Title

Location

Bio

Publications

Challenges and Opportunities for Stacked Transistor: DTCO and Device

Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel

Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors

Selective Enablement of Dual Dipoles for near Bandedge Multi-Vt Solution in High Performance FinFET and Nanosheet Technologies

A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices

Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications

Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm

Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction

Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor

Patents

High-k Dielectric Gate Structures Resistant To Oxide Growth At The Dielectric/silicon Substrate Interface And Methods Of Manufacture Thereof

Device Structure, Layout And Fabrication Method For Uniaxially Strained Transistors

Nanopillar Decoupling Capacitor

Integration Of Passive Device Structures With Metal Gate Layers

Cmos Transistors With Differential Oxygen Content High-k Dielectrics

High-k Metal Gate Cmos

Direct Contact Between High-k/metal Gate And Wiring Process Flow

Cmos Transistors With Differential Oxygen Content High-k Dielectrics

Cmos Transistors With Differential Oxygen Content High-k Dielectrics

Top collaborators

Dechao Guo

Hemanth Jagannathan

Miaomiao Wang

Dan J. Dechene