Huiming Bu

Overview

Title

Vice President: IBM Semiconductors Global R&D and Albany Operations

Location

IBM Research - Albany Albany, NY USA

Bio

Dr. Huiming Bu is responsible for IBM global Semiconductor R&D strategy across world-wide labs. He oversees R&D activities in advanced logic, chiplet and advanced packaging, emerging memory and analog AI hardware at IBM Research. In addition to leading semiconductor technology R&D agenda, Huiming is also responsible for IBM Research Albany Lab site and fab operations.

Huiming has ~20 years of professional experience in semiconductor technology R&D at IBM after he received his Ph.D. in Electrical Engineering from Yale University. Huiming has authored/co-authored 100+ technical publications and holds 100+ patents in semiconductor domain.

Huiming started his technical career at IBM on High-κ/Metal Gate project and then led SOI FinFET research and early development for IBM’s 14nm node technology. After that, Huiming and his team delivered 10nm/7nm technology R&D for IBM and its Joint Development Alliance (JDA) partners. They are now working on 2nm development and 1nm & beyond pathfinding R&D. Recently, as IBM formed Semiconductors division under IBM Research, the footprint has expanded from advanced logic to chiplet & advanced packaging, intelligent fab, cloud based EDA and design.

Publications

Backside power distribution for nanosheet technologies beyond 2nm
- - Ruilong Xie
  - Wonhyuk Hong
  - et al.
- 2024
- VLSI Technology and Circuits 2024
Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
- - Shogo Mochizuki
  - Nicolas Loubet
  - et al.
- 2023
- IEDM 2023
Vertical-Transport Nanosheet Technology for Scaling beyond the Lateral-Transport Devices CMOS Era
- - Hemanth Jagannathan
  - Susan Fan
  - et al.
- 2023
- SSDM 2023
The future transistors
- - Wei Cao
  - Huiming Bu
  - et al.
- 2023
- Nature
Next-Generation Logic Design Architecture for Vertical-Transport Nanosheets
- - Biswanath (Biswa) Senapati
  - Jeongho Do
  - et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology
- - Gen Tsutsui
  - Seunghyun Song
  - et al.
- 2022
- IEDM 2022
Critical Elements for Next Generation High Performance Computing Nanosheet Technology
- - R. Bao
  - C. Durfee
  - et al.
- 2021
- IEDM 2021
Gate-Last IO Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic Technologies
- - M. Bhuiyan
  - M. Kim
  - et al.
- 2021
- IEDM 2021
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- - H. Jagannathan
  - B. Anderson
  - et al.
- 2021
- IEDM 2021
Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
- - Curtis Durfee
  - Subhadeep Kal
  - et al.
- 2021
- ECS Meeting 2021

Patents

- 27 Nov 2012
- US
- 8318565
High-k Dielectric Gate Structures Resistant To Oxide Growth At The Dielectric/silicon Substrate Interface And Methods Of Manufacture Thereof
- 16 Oct 2012
- US
- 8288218
Device Structure, Layout And Fabrication Method For Uniaxially Strained Transistors
- 04 Sep 2012
- US
- 8258037
Nanopillar Decoupling Capacitor
- 17 Jan 2012
- US
- 8097520
Integration Of Passive Device Structures With Metal Gate Layers
- 11 Oct 2011
- US
- 8035173
Cmos Transistors With Differential Oxygen Content High-k Dielectrics
- 17 May 2011
- US
- 7943460
High-k Metal Gate Cmos
- 04 Jan 2011
- US
- 7863123
Direct Contact Between High-k/metal Gate And Wiring Process Flow
- 08 Dec 2010
- CN
- ZL200810125977.0
Cmos Transistors With Differential Oxygen Content High-k Dielectrics
- 13 Apr 2010
- US
- 7696036
Cmos Transistors With Differential Oxygen Content High-k Dielectrics

Top collaborators

Huiming Bu

Overview

Title

Location

Bio

Publications

Backside power distribution for nanosheet technologies beyond 2nm

Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology

Vertical-Transport Nanosheet Technology for Scaling beyond the Lateral-Transport Devices CMOS Era

The future transistors

Next-Generation Logic Design Architecture for Vertical-Transport Nanosheets

Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology

Critical Elements for Next Generation High Performance Computing Nanosheet Technology

Gate-Last IO Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic Technologies

Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices

Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors

Patents

High-k Dielectric Gate Structures Resistant To Oxide Growth At The Dielectric/silicon Substrate Interface And Methods Of Manufacture Thereof

Device Structure, Layout And Fabrication Method For Uniaxially Strained Transistors

Nanopillar Decoupling Capacitor

Integration Of Passive Device Structures With Metal Gate Layers

Cmos Transistors With Differential Oxygen Content High-k Dielectrics

High-k Metal Gate Cmos

Direct Contact Between High-k/metal Gate And Wiring Process Flow

Cmos Transistors With Differential Oxygen Content High-k Dielectrics

Cmos Transistors With Differential Oxygen Content High-k Dielectrics

Top collaborators

Dechao Guo

Hemanth Jagannathan

Miaomiao Wang

Dan J. Dechene