We report our investigation of challenges and opportunities for vertically stacked transistors, with a focus on block-level scaling and device performance consideration. At the standard cell level, our DTCO innovation of splitting the power rails can free up a metal track for signal routing. Implementing two circuit rows for complex cells also increases available tracks. At the block level, we performed the routing study through PnR and overcome the shortage of pin access by DTCO innovations, achieving 0.55x area scaling vs non-stack technology. For device design, choices of device structures and materials are evaluated. SiGe FinFET(p) on Nanosheet(n) is identified as a strong candidate for vertically stacked device architecture. MOL resistance with one-sided power rail is found to be a bottleneck limiting the device performance. Double-sided power rail is introduced for the first time in this work to effectively address the MOL resistance for stacked transistors.