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    Enabling multi die chiplet architectures for next generation AI accelerators by developing differentiated interconnect technologies in an open ecosystem.


    Vertical 3D integration provides a new paradigm to enable semiconductor innovations for the next decade. AI accelerators are high performance parallel computation machines that require high bandwidth interconnectivity to many computing components. 3D chiplet technology provides a path to meet these performance demands by bringing multiple technologies together at the package level to increase performance and reduce cost. IBM research is working on high density interconnects, new I/O interfaces, 3D stacking and advanced assembly to meet the AI compute needs. 3D chip stacking optimizes silicon functionality per unit area and increases overall interconnect density beyond what is achievable with traditional scaling. Our next level demonstration will showcase the integration and reliability for 3D chip stacks incorporating Nanosheet logic devices. IBM’s differentiated technology offering includes the pioneering use of IR laser debonding with silicon handler wafers to open up new grindside process capabilities compared to the industry standard of using glass carrier wafers. For maximized interconnectivity we will continue to scale TSV dimensions integrated on a die towards a wafer hybrid bonding vehicle.

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