Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Publications
22 results for Dan J. Dechene
Challenges and Opportunities for Stacked Transistor: DTCO and Device
- J. Wang
- S.D. Suk
- et al.
- 2021
- VLSI Technology 2021
Comprehensive BEOL Performance Assessment: Interconnects Optimized for Signal Routing and Power Delivery in Advanced CMOS Technology Nodes (Invited)
- Nicholas A. Lanzillo
- Rwik Sengupta
- et al.
- 2020
- IITC 2020
Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications
- Ruqiang Bao
- Reinaldo A. Vega
- et al.
- 2019
- IEDM 2019
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Spin-dependent electron scattering in cobalt interconnects
- Nicholas A. Lanzillo
- P. Bhosale
- et al.
- 2019
- Journal of Physics D: Applied Physics
Computational lithography platform for 193i-guided directed self-assembly
- Kafai Lai
- Melih Ozlem
- et al.
- 2014
- SPIE Advanced Lithography 2014
Energy-aware resource allocation strategies for LTE uplink with synchronous HARQ constraints
- Dan J. Dechene
- Abdallah Shami
- 2014
- IEEE TMC
Your worst Nightmare - Inspection of aggressive OPC on 14 nm masks with emphasis on defect sensitivity and wafer defect print predictability
- Karen D. Badger
- Michael Hibbs
- et al.
- 2013
- SPIE Photomask Technology 2013
Two-dimensional mask effects at the 14 nm logic node
- A.E. Zweber
- A.E. McGuire
- et al.
- 2013
- SPIE Photomask Technology 2013