Comprehensive BEOL Performance Assessment: Interconnects Optimized for Signal Routing and Power Delivery in Advanced CMOS Technology Nodes (Invited)

Abstract

We analyze the impact of interconnect resistance on power delivery network performance using circuit-level simulation for beyond 7 nm technology nodes. We assess the impact of alternate conductors on wide line delay and find between 10-20% performance penalty relative to Cu. In addition, we assess the performance impact of a backside power rail (BPR) and find up to a 25% reduction in delay at a fixed power tap spacing, or equivalently a 1.5x increase in power tap spacing at a fixed voltage (IR) drop. We find that IR drop along power lines can vary from ~10 mV to ~100 mV depending on power tap frequency, inverter drive strength and activity factor.