Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- Nick Lanzillo
- Jim Mazza
- et al.
- 2025
- IEDM 2025
Conference paper
Publications
23 results for Dan J. Dechene
NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- S. Reboh
- C. Zhang
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paperBackside Routing Enablement Considerations For Advanced Node GAA Devices
- Kumar Subramani
- Rwik Sengupta
- et al.
- 2025
- VLSI Technology and Circuits 2025
Invited talkMonolithic Stacked FET with Stepped Channels for Future Logic Technologies
- Chen Zhang
- Seungmin Song
- et al.
- 2024
- IEDM 2024
Conference paperBackside power distribution for nanosheet technologies beyond 2nm
- Ruilong Xie
- Wonhyuk Hong
- et al.
- 2024
- VLSI Technology and Circuits 2024
Conference paperDTCO Guided Process Integration: Case Studies from FEOL & BEOL with BSPDN Topic: DTCO/DFM
- Minhaz Abedin
- Shahrukh Khan
- et al.
- 2024
- ASMC 2024
Conference paperDTCO Guided Process Integration: Case Studies From FEOL & BEOL with BSPDN
- Minhaz Abedin
- Shahrukh Khan
- et al.
- 2024
- ASMC 2024
Conference paperMethodology Development to Benchmark Power Delivery Designs in Advanced Technology Nodes
- Nicholas A. Lanzillo
- A. Chu
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Conference paperNext-Generation Logic Design Architecture for Vertical-Transport Nanosheets
- Biswanath (Biswa) Senapati
- Jeongho Do
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Invited talkBenchmarking Power Delivery Network Designs at the 5-nm Technology Node
- Nicholas A. Lanzillo
- Albert M. Chu
- et al.
- 2021
- IEEE T-ED
Paper